1. Field of the Invention
The field of the invention relates to the field of data storage and in particular, to the storage and access of data in semiconductor memories.
2. Description of the Prior Art
With ever increasing demands to reduce both the size of devices and their power consumption, it is becoming increasingly challenging to design robust semiconductor memories such as SRAM. Each storage cell in an SRAM comprises a feedback loop for holding a data value. In order to write to the feedback loop and store a new value, the input data value must have a high enough voltage level to be able to switch the state stored by the feedback loop if required, while reading from the feedback loop should be performed without disturbing the values stored in any of the feedback loops. When reading from a cell both bit lines are pre-charged and the side of the cell storing a 0 will pull down the bit line it is connected to and this change in voltage level can be detected to determine where the 0 is stored. However, the difference in voltage levels between the precharged bit line and the 0 may result in the node storing a 0 being pulled up towards 1 resulting in instability in the bit cell and the bit cell flipping value. This is called read disturb and can happen to a cell during a read to a cell or during a write to another cell on the same word line. In the latter case the word line is activated to access the cell being written to, which affects other cells connected to the word line.
As dimensions scale down the variations in device properties due to random dopant fluctuations, line edge roughness etc. increase drastically.
Thus, designing a robust SRAM where cells can be read (without read disturb) and written to across all operational voltage ranges turns out to be very difficult. Reducing the voltage at which the SRAM cells can be read and written to successfully is not easy and in particular as the voltage scales down it becomes increasingly difficult to write to the cells.
It would be desirable to be able to reduce both read and write failures of a semiconductor memory.